This invention is directed to metal-oxide-semiconductor memory devices, and more particularly, to a method of operating an array of random access memory cells where the memory cell is a single MOS transistor.
The earliest semiconductor memories were bipolar, usually transistor - transistor logic (TTL), and were limited in the number of bits. With the development of the MOS technologies bit density has increased dramatically. At the present time N-channel MOS memories are being regularly fabricated with 16,384 bits of memory, and devices with 65,536 bits of memory are beginning to reach the market. Even higher density memories are in the design phase. To meet the demands for high density memories new technologies and device designs have been necessary. Originally, most MOS dynamic RAM's used a three transistor memory cell. This cell is too large for present designs. Today the one transistor-one capacitor cell is standard. Future designs will utilize memory cells using only a single MOS transistor. A one transistor memory cell, similar to the photodetector structure in U.S. Pat. No. 4,000,504 by Berger, is used in the array of the present invention. That structure, however, cannot be used in a memory array without significant changes in its method of operation. Berger's structure, designed as a photodetector uses only the gate electrode to attract or remove holes from beneath the gates. Of course a single electrode cannot be used to select a single cell out of a large array without disturbing other cells.